Tuesday, May 11

Optimization in Circuit Placement for VLSI

3:30 PM-5:30 PM
Room: Atlanta 4

The 1997 National Technology Roadmap for Semiconductors predicts that exponential scaling of on-chip integration will continue for at least a decade, leading to chips with over half a billion transistors operating at 2-3 GHz. Existing IC placement techniques have limitations in handling both spatial nonoverlapping constraints and timing constraints efficiently during global optimization of the placement solutions. There has been little fundamental algorithmic advancement in the past decade since the adoption of the simulated annealing and quadratic placement techniques in the 1980s. The speakers in this minisymposium will present recent results on new, efficient, and scalable solutions to large-scale IC placement under tight timing constraints.

Organizers: Joseph R. Shinnerl and Jason Cong
University of California, Los Angeles

3:30-3:55 Placement Using Mathematical Optimization Techniques
Bill Halpin, Lynn Qian and Bala R. Thumma, Intel Corporation
4:00-4:25 A New Partitioning Approach for Large-Scale Circuit Placement
Jens Vygen, University of Bonn, Germany
4:30-4:55 Effective Optimization Strategies for Large-Scale VLSI Placement
UpdatedAndrew B. Kahng, University of California, Los Angeles; Andrew A. Kennings, Ryerson Polytechnic University , Ontario, Canada; and Igor Markov, University of California, Los Angeles
5:00-5:25 A Nonlinear Programming Approach to Circuit Placement
Tony F. Chan, Jason Cong, and Tianming Kong, University of California, Los Angeles; Joseph R. Shinnerl, Organizer, and Dongmin Xu, University of California, Los Angeles

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