Trumping the Multicore Memory Hierarchy with Hi-Spade

Date-intensive applications demand effective use of the cache/memory/storage hierarchy of the target computing platform(s) in order to achieve high performance. Algorithm designers and application/system developers, however, tend towards one of two extremes: (i) they ignore the hierarchy, programming to the API view of "memory + I/O" and often ignoring parallelism; or (ii) they are (pain)fully aware of all the details of the hierarchy, and hand-tune to a given platform. The former often results in very poor performance, while the latter demands high programmer effort for code that requires dedicated use of the platform and is not portable across platforms. Moreover, two recent trends---pervasive multi-cores and pervasive flash---provide both new challenges and new opportunities for maximizing performance.

In the Hi-Spade (Hierarchy-Savvy parallel algorithm design) project, we are developing a hierarchy-savvy approach to algorithm design and systems for these emerging parallel hierarchies. The project seeks to create abstractions, tools and techniques that (i) assist programmers and algorithm designers in achieving effective use of emerging hierarchies, and (ii) leads to systems that better leverage the new capabilities these hierarchies provide. Our abstractions seek a sweet spot between ignoring and (pain)fully aware, exposing only what must be exposed for high performance, while our techniques aim to deliver that high performance across a variety of platforms and platform-sharing scenarios. Key enablers of our approach include novel thread schedulers and novel uses of available flash devices. This talk summarizes our progress to date towards achieving our goals and the many challenges that remain.

Phillip Gibbons, Intel Labs Pittsburgh

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